Semiconductor integrated circuit device and method of manufacturing thereof

ABSTRACT

A semiconductor integrated circuit device comprises an integrated circuit portion, a fuse element block, and a data transfer selecting circuit. The fuse element block includes a programmable fuse element. The data transfer selecting circuit selects one of the transfer of data programmed in the fuse element to the integrated circuit portion, transfer of data input from outside to the integrated circuit portion, and transfer of data programmed in the fuse element to outside.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2000-305402, filed Oct.4, 2000, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integratedcircuit device, more specifically, the invention relates to asemiconductor memory device capable of trimming of chip internal timingby fuse blow and redundancy replacement.

[0004] 2. Description of the Related Art

[0005] In recent year, along with the ultra fine level of semiconductormanufacturing processes and the high speed of semiconductor memorydevices to meet the high speed of system clocks, action margin incircuits has become small and it has been very difficult to optimizecircuit actions.

[0006] Further, process fluctuations owing to complicated manufacturingprocesses have caused characteristics of transistor and resister to goout of the initial design targets, which in turn has made it moredifficult to optimize circuit actions.

[0007] For the purpose of the optimization of circuit actions and theimprovement of yield, in ordinary cases, in consideration of theinfluences by these process fluctuations and the like, a fuse set fortrimming circuit characteristics and a fuse set for replacing redundancyof queue addresses are arranged in a chip.

[0008] With respect to fuses, a laser fuse wherein a fuse ofpolysilicon, metal and the like is blown by a laser beam is generallyemployed, while with a laser fuse, it is not possible to trim a chipafter packaging, as a result, in recent years, an electric fuse whereina fuse can be blown electrically even after packaging has come to beemployed in chips.

[0009]FIG. 15 is a block diagram showing a typical constitution of suchsemiconductor memory device described above.

[0010] As shown in FIG. 15, a semiconductor memory device includes thenumber n of fuses in total, and comprises a fuse set block (Fuse Block)1 that outputs fuse data F<n> for trimming circuit characteristics, aclock generating circuit (Control Clock Generator) 2 that can trim thegeneration timing of an internal clocks CLK_P/CLK_O/CLK_I to controlactions of chip inside, a peripheral circuit 3 that is controlled by theinternal clocks CLK_P/CLK_O/CLK_I generated from the clock generatingcircuit 2, an I/O circuit 4 consisting of 2 circuits, i.e., a dataoutput buffer (Data Out Buffer) and a data input buffer (Data InBuffer), and a memory cell array 5 in which data read and write arecontrolled by the circuits 3 and 4 controlled by the internal clocks.

[0011] In the device shown in FIG. 15, the internal clocksCLK_P/CLK_O/CLK_I generated from the clock generating circuit 2 areinternal clocks for controlling the peripheral circuit 3, the dataoutput buffer in the I/O circuit 4, and the data input bufferrespectively.

[0012] The peripheral circuit 3 works in synchronization with theinternal clock CLK_P, therefore, by changing the generating timing ofthe clock CLK_P, the action timing in the peripheral circuit 3 may bechanged optionally.

[0013] The data output buffer is a circuit for reading data from thememory cell array to the outside of the chip in synchronization with arise edge or a fall edge, or both the edges of the internal clock CLK_O,and by changing the generating timing of the clock CLK_O, it is possibleto adjust the timing of data output in optional manners.

[0014] While, the data input buffer is a circuit for take data to bewritten into the memory cell array into the inside of the chip insynchronization with the rise edge, or the fall edge, or both the edgesof the internal clock CLK_I, and by changing the generating timing ofthe clock CLK_I, it is possible to adjust the timing of data input inoptional manners.

[0015] In the next place, the whole actions will be explained with thecase of trimming of data input timing as an example.

[0016]FIG. 16A is a diagram showing a relation between an external clockCLK and data DQ, FIG. 16B is a diagram showing a relation between aninternal clock CLK_I and an input data D_IN (before trimming), and FIG.16C is a diagram showing a relation between an internal clock CLK_I andan input data D_IN (after trimming).

[0017] As shown in FIG. 16A, the write data to the memory cell array isinput from DQ PAD in synchronization with both the rise edge and thefall edge of the external clock CLK. At this moment, data is input atthe timing at which the circuit action margin of the data input bufferbecomes maximum to the clock. Namely, when a clock cycle is referred toas T, data is input at the timing at which a set up time Ts of certaininput data to the clock and a hold time Th should become T/4.

[0018] In this way, the relation between the clock and the data isoptimized at the outside of the chip, however in the actual inside ofthe chip, such an ideal relation is in fact not attained. This isbecause there is delay in the generating timing of the internal clockCLK_I owing to process fluctuations, and under the influences of LCRinside of the chip.

[0019] Now, it is assumed that the timing of the internal clock CLK_I isdisplaced by +Δt from the factors mentioned above. In this case, asshown in FIG. 16B, a setup time TSi of data input to the chip internaldata D_IN becomes T/4+Δt, and the circuit action margin widens, while ahold time Thi of the data input becomes T/4−Δt, and the circuit actionmargin become small, different from the former case.

[0020] In order to correct such imbalance of the circuit action margin,a fuse that fastens the generating timing of the internal clock CLK_I by−Δt is blown, thereby the internal clock CLK_I is trimmed, and as shownin FIG. 16C, the internal timing is coordinated with the externaltiming, and thereby the circuit actions are optimized.

[0021] However, since an actual chip is subject to the influence ofprocess fluctuations, even when an identical fuse is blown, a trimmingvalue is not always same, which is the fact at present.

[0022] Accordingly, a trimming method by the fuse blow mentioned abovehas held a problem that the trimming effect by fuse blow, i.e., whetherthe blown fuse is actually optimized to the chip concerned or not, canbe known only after the fuse concerned is actually blown. As aconsequence, trimming amount may be in short, or to excess in cases.

[0023] In other words, in the method for trimming by fuse blow in theprior art, it has been extremely difficult to carry out the optimizedtrimming to a chip, which has been a problem in the prior art.

[0024] In the method by laser fuse blow carried out before packaging, itis easily confirmed whether a fuse concerned is blown correctly or not,while when using the electric fuse after packaging a chip, there is nomeans for judging whether the fuse is blown correctly or not, therefore,it is not to be known until the chip is tested in actual manners, whichhas been another problem with the prior art.

[0025] The above is the case concerning the trimming of clock generatingtiming, but the conditions are same also in the cases of redundancyreplacement of queue addresses.

[0026] In general, in the replacement of queue addresses by redundancy,before carrying out fuse blow, a test is carried out on a redundancyarray to be determined by the queue address to be replaced, and on thebasis of the result thereof, redundancy replacement is carried out.

[0027] The redundancy cell test is only for testing whether a cell isvalid or not, therefore, the test is nor carried out by making a chipwork at the same timing as an actual test.

[0028] Consequently, there may be cases where a test is made afterredundancy replacement, action is not made correctly owing to mismatchin timing and the like.

[0029] The above inconvenience, as well as the case of the above clockgenerating timing, comes from the fact that by the current trimmingmethod by fuse blow and the method of redundancy replacement, it is notpossible to judge the conditions of a chip after fuse blow, until thefuse is actually blown, which has been still another problem in theprior art.

BRIEF SUMMARY OF THE INVENTION

[0030] A semiconductor integrated circuit device according to anembodiment of the present invention comprises: an integrated circuitportion; a fuse element block including a programmable fuse element; anda data transfer selecting circuit that selects any one of transfer ofdata programmed in the fuse element to the integrated circuit portion,transfer of data input from outside to the integrated circuit portion,and transfer of data programmed in the fuse element to outside.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0031]FIG. 1 is a block diagram showing a configuration example of asemiconductor integrated circuit device according to a first embodimentof the present invention.

[0032]FIG. 2A is a signal waveform diagram showing an example of arelation between an external clock CLK and data DQ.

[0033]FIG. 2B is a signal waveform diagram showing an example of arelation between an internal clock CLK_I and input data D_IN (beforetrimming).

[0034]FIG. 2C is a signal waveform diagram showing an example of arelation between an internal clock CLK_I and input data D_IN (aftertrimming).

[0035]FIG. 3 is a circuit diagram showing a circuit example of atrimming register circuit 6.

[0036]FIG. 4A is a circuit diagram showing a circuit example of atrimming block selecting circuit 13.

[0037]FIG. 4B is a table showing an example of the results ofcalculations of a data transfer control logic section.

[0038]FIG. 5 is a diagram showing an example of a condition of a datatransfer circuit 14 in a Normal state.

[0039]FIG. 6 is a diagram showing an example of a condition of a datatransfer circuit 14 in a Write state.

[0040]FIG. 7 is a diagram showing an example of a condition of a datatransfer circuit 14 in a Read state.

[0041]FIG. 8 is a circuit diagram showing a circuit example of a fuseset block 1.

[0042]FIG. 9 is a block diagram showing an example of a relation betweena trimming register 12 and a trimming block 11.

[0043]FIG. 10 is a circuit diagram showing a circuit example of thetrimming register 12.

[0044]FIG. 11 is a flow chart showing an example of a trimming methodusing the semiconductor integrated circuit device according to the firstembodiment of the present invention.

[0045]FIG. 12A is a block diagram showing a configuration example of asemiconductor integrated circuit device according to a second embodimentof the present invention.

[0046]FIG. 12B is a diagram showing a configuration example of a fuseset block which the semiconductor integrated circuit device according tothe second embodiment of the present invention.

[0047]FIG. 13A is a block diagram showing a configuration example of asemiconductor integrated circuit device according to a third embodimentof the present invention.

[0048]FIG. 13B is a diagram showing a configuration example of a fuseset block which the semiconductor integrated circuit device according tothe third embodiment of the present invention has.

[0049]FIG. 14 is a block diagram showing a configuration example of asemiconductor integrated circuit device according to a fourth embodimentof the present invention.

[0050]FIG. 15 is a block diagram showing a typical semiconductorintegrated circuit device.

[0051]FIG. 16A is a diagram showing a relation between an external clockCLK and data DQ.

[0052]FIG. 16B is a diagram showing a relation between an internal clockCLK_I and input data D_IN (before trimming).

[0053]FIG. 16C is a diagram showing a relation between an internal clockCLK_I and input data D_IN (after trimming).

DETAILED DESCRIPTION OF THE INVENTION

[0054] Hereinafter, embodiments of the present invention will beexplained with reference to the accompanying drawings. In theexplanation, like parts in each of the several figures are identified bythe same reference numerals.

[0055] (First Embodiment)

[0056]FIG. 1 is a block diagram showing a constitution of asemiconductor integrated circuit device according to a first embodimentof the present invention.

[0057] As shown in FIG. 1, a fuse set block (Fuse Block) 1 includes thenumber n in total of fuses to be blown by laser, or electric means suchas electric current and the like, and outputs a parallel fuse dataF<1:n> that shows whether the fuses are blown or not. The parallel fusedata F<1:n> is used as data for trimming circuit characteristics.

[0058] A clock generating circuit (Control Clock Generator) 2 receivesan external clock signal CLK1, and generates a plurality of internalclock signals CLK_P/CLK_O/CLK_I that controls actions inside of a chip.The clock generating circuit 2 trims the generating timing of the aboveinternal clocks CLK_P/CLK_O/CLK_I into the optimized value on the basisof the above fuse data F<1:n>.

[0059] A peripheral circuit 3, whose actions are controlled by theinternal clock signal CLK_P generated by the clock generating circuit 2,takes in an external command signal in synchronization with the internalclock signal CLK_P, and carries out calculations, and generates aplurality of address signals of queue and a plurality of internalcontrol signals.

[0060] An I/O circuit 4 includes: a data input buffer (Data In Buffer)that, in synchronization with the internal clock signal CLK_I generatedby the clock generating circuit 2, takes in an external serial datasignal having a data width of, for example, q bits and transfers theexternal serial data signal to an internal serial data signal linehaving a data width of q bits; and a data output buffer (Data OutBuffer) that, in synchronization with the internal clock signal CLK_Ogenerated by the clock generating circuit 2, takes in an internal serialdata signal having a data width of, for example, q bits and transfersthe internal serial data signal to an external serial data signal linehaving a data width of q bits.

[0061] A memory cell array 5 comprises a plurality of memory cellsselected by a plurality of address signals. Reading data from andwriting data into the memory cell array 5 is controlled by theperipheral circuit 3 and the I/O circuit 4.

[0062] Further, the device according to the present embodiment includesa trimming register circuit (Trimming Register Block) 6 that outputs atrimming data signal Ft<n> that trims the generating timing of theinternal clock signals CLK_P/CLK_O/CLK_I generated by the clockgenerating circuit 2.

[0063] The trimming register circuit 6 converts and outputs any one ofthe parallel fuse data F<1:n> output from the fuse set block 1 and adata-rewritable and parallel data R<1:n> transferred from a trimmingregister (whose detailed described hereinafter) arranged in the trimmingregister circuit 6 as a trimming data Ft<1:n>.

[0064] In the device shown in FIG. 1, the internal clocksCLK_P/CLK_O/CLK_I generated from the clock generating circuit 2 areinternal clocks for controlling the peripheral circuit 3, the dataoutput buffer in the I/O circuit 4, and the data input bufferrespectively.

[0065] In the device according to the present embodiment, as shown inFIGS. 2A to 2C, as same as in the prior art, by changing the internalclock generating timing, it is possible to adjust the action timing inthe peripheral circuit 3, the data input timing, and the data outputtiming to the optimized values.

[0066] Hereafter the trimming register circuit 6 in the presentembodiment will be explained.

[0067]FIG. 3 is a circuit diagram showing a circuit constitution exampleof the trimming register circuit 6 according to the present invention.

[0068] As shown in FIG. 3, the trimming register circuit 6 in thepresent embodiment comprises three circuits, i.e., trimming blocks(Trimming Block 1 to Trimming Block 3) 11-1 to 11-3, a trimming register(Trimming Register) 12 that can freely read and write data of n bits,and a trimming block (Trimming Block) selecting circuit 13.

[0069] The trimming blocks (Trimming Block) 11-1 to 11-3 are divided forCLK_O, for CLK_I, and for CLK_P, and each of them comprises the number nof data (Data) transfer selecting circuits 14-1 to 14-n same as thenumber of bits necessary for trimming the internal clocksCLK_O/CLK_P/CLK_I.

[0070] Each of the number n of the data transfer selecting circuits 14-1to 14-n that output the trimming data Ft<1:n> of n bits comprises twotransfer gates, and controls outputting either the data F<1:n> from thefuse set or the data R<1:n> from the trimming register 12 as trimmingdata Ft<1:n>.

[0071] The control over a gate level of transfer gates in the datatransfer selecting circuits 14-1 to 14-n, and the selection of thetrimming blocks 11-1 to 11-3 are made by four control signalsPG1/NG1/PG2/NG2 output from the trimming block selecting circuit 13.

[0072] The trimming register 12 is a read and write register of bit ofthe same number as the number of bits necessary for trimming theinternal clocks CLK_O/CLK_P/CLK_I.

[0073] The trimming block selecting circuit 13 creates control signalsPG1/NG1/PG2/NG2 for selecting the trimming blocks 11-1 to 11-3corresponding to the internal clock that carries out trimming.

[0074] The trimming blocks 11-1 to 11-3 are divided into three states,i.e., (1) Normal state, (2) Write state, and (3) Read state according tothe conditions of the above four control signals PG1/NG1/PG2/NG2.

[0075] In the next place, the trimming block selecting circuit 13 willbe explained.

[0076]FIG. 4A is a diagram showing an example a circuit constitution ofa trimming block selecting circuit 13 according to the presentembodiment.

[0077] As shown in FIG. 4A, the trimming block selecting circuit 13 inthe present embodiment comprises a trimming block selecting register(Trimming Block Selecting Register) 21, and data transfer control logicsections (Data Transfer Control Logic section 1 to Data Transfer ControlLogic section 3) 22-1 to 22-3.

[0078] The data transfer control logic sections 22-1 to 22-3 are dividedinto three corresponding to the above trimming blocks 11-1 to 11-3. Theconditions of the data transfer control logic sections 22-1 to 22-3 aredetermined by address signals (Add1/Add2) of 2 bits output from thetrimming block selecting register 21, and a mode signal Read thatdetermines the conditions of the trimming blocks.

[0079]FIG. 4B shows an example of the results of calculations of thedata transfer control logic section 22-3 to the trimming block 11-2 forthe internal clock CLK_I.

[0080] As shown in FIG. 4B, when both the addresses Add1/Add2 from thetrimming block selecting register 21 are not “HIGH”, the trimming block11-2 gets always in the Normal state. On the contrary, when both theaddresses Add1/Add2 are “HIGH”, the trimming block 11-2 gets in Readstate if the mode signal Read is “HIGH”, while in Write state if themode signal Read is “LOW”.

[0081] It is determined which of the trimming blocks 11-1 to 11-3 isselected according to the conditions of the addresses Add1/Add2 inputinto a NAND logic circuit in the data transfer control logic sections22-1 to 22-3.

[0082] Hereafter there will be explained the three states of thetrimming block 11, i.e., (1) Normal state, (2) Write state, and (3) Readstate.

[0083] First (1) Normal state will be explained. FIG. 5 shows acondition of the data transfer circuit 14 in the Normal state.

[0084] In the (1) Normal state, as shown in FIG. 5, a transfer gate TRS1is in an ON state, while a transfer gate TRS2 is in an OFF state. Forthis reason, trimming data Ft output to the clock generating circuit 2becomes data F from the fuse set block 1, and the trimming of theinternal clocks is made on the basis of the data F.

[0085] Next, the (2) Write state will be explained hereafter. FIG. 6shows a condition of the data transfer selecting circuit 14 in thetrimming clock 11 in the Write state.

[0086] In the (2) Write state, as shown in FIG. 6, the transfer gateTRS1 is in the OFF state, while the transfer gate TRS2 is in the ONstate. For this reason, the trimming data Ft output to the clockgenerating circuit 2 becomes data R from the trimming register 12. Thedata R from the trimming register 12 may be set freely by writing datainto the trimming register 2 from, for example, an external pad RIO.Therefore, it is possible to freely carry out the trimming of theinternal clocks.

[0087] In the next place, the (3) Read state will be explained. FIG. 7shows a condition of the data transfer circuit 14 in the trimming block11 in the Read state.

[0088] In the (3) Read state, as shown in FIG. 7, both the transfergates TRS1 and TRS2 are in ON state. As a result, the trimming data Ftoutput to the clock generating circuit 2 becomes data F from the fuseset block 1.

[0089] In this case, since the transfer gate TRS2 is also in the ONstate, it is possible to read the data F from the fuse set block 1,namely, the trimming data Ft, by use of the trimming register 12through, for example, the external pad RIO.

[0090] Then the fuse set block 1 will be explained.

[0091]FIG. 8 is a diagram showing an example of a circuit constitutionof a fuse set block 1 according to the present embodiment.

[0092] As shown in FIG. 8, the fuse set of the present embodimentcomprises a laser fuse block (Laser Fuse Block) 31, and an electric fuseblock (Electric Fuse Block) 32. For example, a laser melt down type fuseis arranged on the laser fuse block 31, while for example, a electriccurrent melt down type fuse is arranged on the electric fuse block 32.

[0093] By such a constitution mentioned above, after a chip is trimmedby a laser fuse before packaging, even if it is required to carry outre-trimming owing to influence by packaging, it is possible to carry outtrimming.

[0094] Next, the trimming register 12 will be explained.

[0095]FIG. 9 is a diagram showing a relation between the trimmingregister 12 and the trimming block 11 in the present embodiment, whileFIG. 10 is a diagram showing an example of a circuit constitution of thetrimming register 12. By the way, in this circuit configuration example,it is supposed that trimming data Ft is of 8 bits.

[0096] As shown in FIG. 9 and FIG. 10, the trimming register 12 includeseight flip flop (FF) circuits 41-1 to 41-8, eight multiplex (MX)circuits 42-1 to 42-8, eight Write output circuits 43-1 to 43-8, and aRead output circuit 44.

[0097] Each output node fuse<1:n> of the flip flop circuits 41-1 to 41-8in this configuration example of the circuit is connected to a firstinput of the multiplex circuits 42-1 to 42-8, and also connected toinputs of the Write output circuits 43-1 to 43-8.

[0098] Each output of the Write output circuits 43-1 to 43-8 isconnected to a connection node dREGbit<1:n> between the trimmingregister 12 and the trimming block. Further, the connection nodedREGbit<1:n> is connected to a second input of the multiplex circuits42-1 to 42-8.

[0099] The multiplex circuits 42-1 to 42-8 respectively select any oneof the output node fuse<1:n> and the connection node dREGbit<1:n> on thebasis of a signal fuse data en, and connect to the inputs of the flipflop circuits 41-2 to 41-8, and the input of the Read output circuit 44.

[0100] The output of the Read output circuit 44 is connected to aconnection node Core Data between the trimming register 12 and theexternal pad RIO. Further, the connection node Core Data is connected tothe input of the flip flop circuit 41-1 at the first stage, among theflip flop circuits 41-1 to 41-8.

[0101] In the next place, actions thereof will be explained.

[0102] At Write process, first, the flip flop circuits 41-1 to 41-8 arereset by use of a reset signal fuse rst.

[0103] Further, the signal fuse data en is set to, for example, “HIGH”so that the multiplex circuits 42-1 to 42-7 respectively select anoutput node fuse<1:7>. By the way, the multiplex circuit 42-8 at thefinal stage is controlled by a signal of phase opposite to that of thefuse data en, and at Write process, it does not select an output nodefuse<8>.

[0104] In this state, data is input in serial manner to the input of theflip flop circuit 41-1 at the initial stage from the external pad RIOvia the connection node Core Data. The flip flop circuits 41-1 to 41-8respectively work in synchronization with a control clock fuse clk, andoutput the input data according to the fall or rise of the control clockfuse clk. For example, by toggling the control clock fuse clk eighttimes, data is set to the respective eight flip flop circuits 41-1 to41-8. After data is set, the signal write is set, for example, “HIGH”level, and the Write output circuits 43-1 to 43-8 are enabledrespectively. As a result, the data set to the flip flop circuits 41-1to 41-8 is output as data R<1:n> to the trimming block 11. Thereby, fromthe trimming block 11, as mentioned above, the data R<1:n> is output asa trimming data Ft<1:n> to the clock generating circuit 2.

[0105] While, at Read process, the flip flop circuits 41-1 to 41-8 arereset by use of the reset signal fuse rst.

[0106] Further, the signal fuse data en is first set, for example,“LOW”, so that the multiplex circuits 42-1 to 42-7 respectively selectthe connection node dREGbit<1:7>. By the way, the multiplex circuit 42-8at the final stage is controlled by a signal of phase opposite to thatof the fuse data en, and at this moment, it does not select a connectionnode dREGbit<8>.

[0107] In this state, the data F<1:7> from the fuse set block 1 is inputto the inputs of the flip flop circuits 41-2 to 41-8 at the initialstage, from the trimming block 11, via the connection node dREGbit<1:7>.

[0108] Then, the signal fuse data en is set from “LOW” into “HIGH”, andthe multiplex circuits 42-1 to 42-7 are made to select the output nodefuse<1:7> respectively. At the same time, the multiplex circuit 42-8 atthe final stage is made to select the connection node dREGbit<8>.Thereby, the data F<8> from the fuse set block 1 is input to the Readoutput circuit 44. In this state, the signal Read is set, for example,“HIGH” level, and the Read output circuit 44 is enabled, thereby thedata F<8> is output via the connection node Core Data to the externalpad RIO.

[0109] Then, the signal fuse data en is set from “HIGH” into “LOW” onceagain, and the multiplex circuit 42-8 at the final stage is made toselect the output node fuse<8>. Thereby, to the Read output circuit 44,the data F<7> from the fuse set block 1 set in the flip flop circuit41-8 is input, and following the data F<8>, the data F<7> is output viathe connection node Core Data from the external pad RIO.

[0110] Hereafter, the above actions are repeated until the data F<1> isoutput, and thereby, the data F<1:8> set in the fuse set block 1 can beread.

[0111] In the next place, the entire actions of the present embodimentare explained hereafter.

[0112] First the case of trimming of data input timing will beexplained. As same as the prior art, when the internal clock CLCK_I isdelayed by +Δt in the chip inside as shown in FIG. 2B, it is required tocarry out trimming to fasten by Δt the generation timing of the internalclock CLK_I by the clock generating circuit.

[0113] When carrying out trimming, in the prior art, it has been notpossible to check actual trimming amount and the like until a fuse isactually blown, while according to the present invention, before a fuseif actually blown, the state of the trimming block 11 of the trimmingregister circuit 6 is set to the Write state, and trimming data same asa trimming forecast value by fuse blow is written in via the trimmingregister 12. Thereby, it is possible to check trimming effects in thesame conditions as fuse blown state.

[0114] At this stage, if it is judged that expected effects are attainedas planned by the trimming data Ft from the trimming register circuit 6,then a fuse may be blown first.

[0115] On the contrary, if it is judged that effects are insufficient orto excess, the trimming data Ft from the trimming register 6 may beadjusted and optimized, and on the basis of the value, a fuse may beblown.

[0116]FIG. 11 shows a flow chart of trimming method in the presentinvention.

[0117] In the case of carrying out trimming by a laser fuse before achip is packaged too, first, trimming is carried out on the basis of thedata from the trimming register circuit 6, and a fuse blow value isdetermined (ST. 1).

[0118] Then, according to the above fuse blow value, a laser fuse isblown (ST. 2), and it is checked whether the fuse has been blowncorrectly or not by use of the trimming register (ST. 3).

[0119] If the fuse has not been blown (NG), then the procedures go backto fuse blow process, where the fuse is blown once again. If it is foundthat the fuse has been blown correctly (OK), then the chip is filledinto the package (ST. 4).

[0120] Then, product test is carried out (ST. 5), and if there is noproblem, products are shipped (ST. 6).

[0121] If trimming is required once again owing to influence ofpackaging (NG), then by use of the trimming register circuit 6, a fusevalue of trimming by an electric fuse is determined (ST. 7).

[0122] In the next place, on the basis of the above fuse value, theelectric fuse is blown (ST. 8), and it is checked whether the fuse hasbeen blown correctly or not by use of the trimming register circuit 6(ST. 9).

[0123] If the fuse has not blown (NG), then the procedures go back tofuse blow process, where the fuse is blown once again. If it is foundthat the fuse has been blown correctly (OK), product test is carried out(ST. 10), and if there is no problem, products are shipped (ST. 11).

[0124] If there is a problem, for example any nonconformity has beenfound (NG), by use of the trimming register circuit 6, a fuse value maybe determined once again.

[0125] From the above, according to the present invention, it ispossible to carry out trimming with the optimized value to all thechips, different from the prior art where it can be found that trimmingeffects are insufficient or to excess only after a fuse is blown.

[0126] Further, according to the present invention, it is possible tocheck whether a fuse has been blown correctly or not even afterpackaging in easy manners by use of the trimming register circuit 6,therefore, in the case of fuse blow by use of an electric fuse, theinvention is also effective in verification of fuse blow.

[0127] By the trimming method shown in FIG. 11, it is possible to remedya device where fuse blow has been incomplete, as a result, it ispossible to increase yield further.

[0128] (Second Embodiment)

[0129]FIG. 12A is a block diagram showing a constitution of asemiconductor integrated circuit device according to a second embodimentof the present invention. FIG. 12B is a diagram showing a constitutionof a fuse set block thereof.

[0130] As shown in FIG. 12A, the semiconductor memory device accordingto the second embodiment, as well as the first embodiment, includes afuse set block 1 having fuse data F<n> of the number n in total of fusesfor circuit characteristic trimming, a clock generating circuit 2 thatcan trim the clock generation timing to the optimized value by the fusedata F<n>, a trimming register circuit 6 that creates a trimming datasignal Ft<n> to control clock generating circuits, a peripheral circuit3 controlled by the internal clock generated by the clock generatingcircuit 2, an I/O circuit 4 consisting of two circuits, i.e., a dataoutput buffer (Data Out Buffer) and a data input buffer (Data InBuffer), and a memory cell array 5 whose data writing and reading arecontrolled by the two circuits controlled by the internal clocks.

[0131] However, in this second embodiment, as shown in FIG. 12B,different from the configuration of the fuse set block 1 in the firstembodiment, the fuse comprises only a laser fuse 31.

[0132] In the semiconductor memory device according to the secondembodiment of the present invention, in the same manner as in the firstembodiment, by use of the trimming register circuit 6, it is possible todetermine the most suitable fuse value by confirming fuse blow effectsin advance, and it is possible to carry out trimming to all the chipswith the most suitable value.

[0133] (Third Embodiment)

[0134]FIG. 13A is a block diagram showing a constitution of asemiconductor integrated circuit device according to a third embodimentof the present invention. FIG. 13B is a diagram showing a constitutionof a fuse set block thereof.

[0135] As shown in FIG. 13A, the semiconductor memory device accordingto the second embodiment, as well as the first embodiment, includes afuse set block 1 having fuse data F<n> of the number n in total of fusesfor circuit characteristic trimming, a clock generating circuit 2 thatcan trim the clock generation timing to the optimized value by the fusedata F<n>, a trimming register circuit 6 that creates a trimming datasignal Ft<n> to control clock generating circuits, a peripheral circuit3 controlled by the internal clock generated by the clock generatingcircuit 2, an I/O circuit 4 consisting of two circuits, i.e., a dataoutput buffer (Data Out Buffer) and a data input buffer (Data InBuffer), and a memory cell array 5 whose data writing and reading arecontrolled by the two circuits controlled by the internal clocks.

[0136] However, in this third embodiment, as shown in FIG. 13B,different from the configuration of the fuse set block in the first andsecond embodiments, the fuse comprises only an electric fuse 32.

[0137] In the semiconductor memory device according to the thirdembodiment of the present invention, in the same manners as in the firstand second embodiments, by use of the trimming register circuit 6, it ispossible to determine the most suitable fuse value by confirming fuseblow effects in advance, and it is possible to carry out trimming to allthe chips with the most suitable value.

[0138] (Fourth Embodiment)

[0139]FIG. 14 is a block diagram showing a constitution of asemiconductor integrated circuit device according to a fourth embodimentof the present invention.

[0140] As shown in FIG. 14, the semiconductor memory device according tothe fourth embodiment includes a fuse set block 1 comprising of thenumber n in total of fuses having fuse data F<n> for circuitcharacteristic trimming, and the number m in total of fuses forredundancy replacement of queue address having fuse data F<m>, a clockgenerating circuit 2 that can trim the clock generation timing to theoptimized value by the fuse data F<n>, a trimming register circuit 6that creates a trimming data signal Ft<n> to control the clockgenerating circuits 2, and a redundancy signal Fr<n> to control theredundancy replacement of queue address, a peripheral circuit 3controlled by the internal clock generated by the clock generatingcircuit 2, and the redundancy signal Fr<m> output from the trimmingregister circuit 6, an I/O circuit 4 consisting of two circuits, i.e., adata output buffer (Data Out Buffer) and a data input buffer (Data InBuffer), and a memory cell array 5 whose data writing and reading arecontrolled by the two circuits controlled by the internal clocks.

[0141] In the semiconductor memory device according to the fourthembodiment of the present invention, in the same manners as in thefirst, second, and third embodiments, by use of the trimming registercircuit 6, it is possible to determine the most suitable fuse value byconfirming fuse blow effects in advance, and it is possible to carry outtrimming to all the chips with the most suitable value.

[0142] Furthermore, in the fourth embodiment, in the case of redundancyreplacement of queue address too, it is possible to carry out testing inthe same conditions as the case where redundancy replacement has beencarried out, by the use of the trimming register circuit, therefore, itis possible to conduct a precise redundancy replacement.

[0143] According to the present invention mentioned heretofore with theabove first to fourth embodiments, when carrying out the trimming ofchip internal timing by fuse blow and the redundancy replacement ofqueue address, before a fuse if blown actually, trimming of internaltiming and redundancy replacement are carried out by use of the registercircuit, and on the basis of the results thereof, a fuse value foractual fuse blow is determined.

[0144] By reading the conditions of fuse by use of the above registercircuit, it is possible to precisely judge whether fuse blow issuccessful or not, and to grasp the redundancy replacement informationper chip. By this method shown and described heretofore, it is realizedto obtain a semiconductor memory device that enables to determine themost suitable fuse value to carry out timing trimming per chip, and tocarry out precise redundancy replacement to queue address.

[0145] As described heretofore, the present invention has been explainedin reference to the first to fourth embodiments thereof, however, thepresent invention may be embodied in other specific forms withoutdeparting from the spirit or essential characteristics thereof.

[0146] It may be well understood by those skilled in the art that theabove respective embodiments may be embodied by single or bycombination.

[0147] Further, each of the embodiments mentioned above includes varioussteps of invention, and by appropriate combinations of a plurality ofstructural components disclosed in each of the embodiments, it ispossible to extract various stages of invention, which is apparent tothose skilled in the art.

[0148] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor integrated circuit devicecomprising: an integrated circuit portion; a fuse element blockincluding a programmable fuse element; and a data transfer selectingcircuit that selects any one of transfer of data programmed in the fuseelement to the integrated circuit portion, transfer of data input fromoutside to the integrated circuit portion, and transfer of dataprogrammed in the fuse element to outside.
 2. The device according toclaim 1, wherein the integrated circuit portion is a control clockgenerating circuit, and the data is trimming data for trimming thetiming of the control clock.
 3. A semiconductor integrated circuitdevice comprising: a fuse element block including a programmable fuseelement; and a register that being able to store data input fromoutside, store data programmed in the fuse element, and outputaccumulated data to outside.
 4. A semiconductor integrated circuitdevice comprising: an integrated circuit portion; a fuse element blockincluding a programmable fuse element; and a register block including aregister and a data transfer selecting circuit, the register being ableto store data input from outside, store data programmed in the fuseelement, and output accumulated data to outside, the data transferselecting circuit to select any one of transfer of data programmed inthe fuse element to the integrated circuit portion, transfer of dataaccumulated in the register to the integrated circuit portion, andtransfer of data programmed in the fuse element to the register.
 5. Thedevice according to claim 4, wherein the integrated circuit portion is acontrol clock generating circuit, and the data is trimming data fortrimming the timing of the control clock.
 6. The device according toclaim 4, wherein the register is a shift register.
 7. The deviceaccording to claim 4, wherein the register enables data serial-parallelconversion, and parallel-serial conversion.
 8. The device according toclaim 7, wherein the register receives data input from the outside inserial manner, and the data transfer selecting circuit transfers datastored in the register to the integrated circuit portion in parallelmanner.
 9. The device according to claim 7, wherein the data transferselecting circuit transfers data programmed in the fuse element to theregister in parallel manner, and the register outputs stored data tooutside.
 10. A semiconductor integrated circuit device comprising: amemory cell array that includes a plurality of memory cells selected bya plurality of address signals; a clock generating circuit that receivesan external clock signal, and generates a plurality of internal clocksignals; a peripheral circuit that takes in an external command signalin synchronization with a first clock signal generated by the clockgenerating circuit, and carries out calculations, and generates aplurality of address signals of the queue and a plurality of internalcontrol signals; an I/O circuit that takes in an external data signal insynchronization with a second clock signal generated by the clockgenerating circuit, and transfers the external data signal to aninternal data signal line, and also takes in an internal data signal insynchronization with a third clock signal generated by the clockgenerating circuit, and transfers the internal data signal to anexternal data signal line; a fuse element block that includes aprogrammable fuse element, and outputs data programmed in the fuseelement; and a trimming register circuit that converts and outputseither the data output from the fuse element block or an optional datainput from outside, as the data for trimming the generation timing ofthe first, second, and third clock signals, to the clock generatingcircuit.
 11. A semiconductor integrated circuit device comprising: amemory cell array that includes a plurality of memory cells selected bya plurality of address signals; a clock generating circuit that receivesan external clock signal, and generates a plurality of internal clocksignals; a peripheral circuit that takes in an external command signalin synchronization with a first clock signal generated by the clockgenerating circuit, and carries out calculations, and generates aplurality of address signals of the queue and a plurality of internalcontrol signals; an I/O circuit that takes in an external data signal insynchronization with a second clock signal generated by the clockgenerating circuit, and transfers the external data signal to aninternal data signal line, and also takes in an internal data signal insynchronization with a third clock signal generated by the clockgenerating circuit, and transfers the internal data signal to anexternal data signal line; a fuse element block that includes aprogrammable fuse element, and outputs data programmed in the fuseelement; and a trimming register circuit that transfers either the dataoutput from the fuse element block or an optional data input fromoutside, as the redundancy replacement data of the memory cell array, tothe peripheral circuit.
 12. A semiconductor integrated circuit devicecomprising: a memory cell array that includes a plurality of memorycells selected by a plurality of address signals of queue; a clockgenerating circuit that receives an external clock signal, and generatesa plurality of internal clock signals; a peripheral circuit that takesin an external command signal in synchronization with a first clocksignal generated by the clock generating circuit, and carries outcalculations, and generates a plurality of address signals of the queueand a plurality of internal control signals; an I/O circuit that takesin an external data signal in synchronization with a second clock signalgenerated by the clock generating circuit, and transfers the externaldata signal to an internal data signal line, and also takes in aninternal data signal in synchronization with a third clock signalgenerated by the clock generating circuit, and transfers the internaldata signal to an external data signal line; a fuse element block thatincludes a programmable fuse element, and outputs data programmed in thefuse element; and a trimming register circuit that converts and outputseither the data output from the fuse element block or an optional datainput from outside, as the data for trimming the generation timing ofthe first, second, and third clock signals, to the clock generatingcircuit, and also transfers either the data output from the fuse elementblock or an optional data input from outside, as the redundancyreplacement data of the memory cell array, to the peripheral circuit.13. The device according to claim 10, wherein the fuse block includesfuse elements whose electrical connection is blown by at least two ormore different forms.
 14. The device according to claim 11, wherein thefuse block includes fuse elements whose electrical connection is blownby at least two or more different forms.
 15. The device according toclaim 12, wherein the fuse block includes fuse elements whose electricalconnection is blown by at least two or more different forms.
 16. Thedevice according to claim 10, wherein the trimming register circuit isconfigured to read out the data output from the fuse element block tooutside.
 17. The device according to claim 11, wherein the trimmingregister circuit is configured to read out the data output from the fuseelement block to outside.
 18. The device according to claim 12, whereinthe trimming register circuit is configured to read out the data outputfrom the fuse element block to outside.
 19. The device according toclaim 10, wherein the trimming register circuit trims, independently orsimultaneously, the generation timing of the first, second, and thirdclock signals generated from the clock generating circuit.
 20. Thedevice according to claim 11, wherein the trimming register circuittrims, independently or simultaneously, the generation timing of thefirst, second, and third clock signals generated from the clockgenerating circuit.
 21. The device according to claim 12, wherein thetrimming register circuit trims, independently or simultaneously, thegeneration timing of the first, second, and third clock signalsgenerated from the clock generating circuit.
 22. The device according toclaim 10, wherein the I/O circuit takes in an external data insynchronization with the rise edge, or the fall edge, or both the edgesof the second internal clock.
 23. The device according to claim 11,wherein the I/O circuit takes in an external data in synchronizationwith the rise edge, or the fall edge, or both the edges of the secondinternal clock.
 24. The device according to claim 12, wherein the I/Ocircuit takes in an external data in synchronization with the rise edge,or the fall edge, or both the edges of the second internal clock. 25.The device according to claim 10, wherein the I/O circuit outputs aninternal data to outside in synchronization with the rise edge, or thefall edge, or both the edges of the third internal clock.
 26. The deviceaccording to claim 11, wherein the I/O circuit outputs an internal datato outside in synchronization with the rise edge, or the fall edge, orboth the edges of the third internal clock.
 27. The device according toclaim 12, wherein the I/O circuit outputs an internal data to outside insynchronization with the rise edge, or the fall edge, or both the edgesof the third internal clock.
 28. The device according to claim 10,wherein the I/O circuit takes in an external data in synchronizationwith the rise edge, or the fall edge, or both the edges of the secondinternal clock, and also outputs an internal data to outside insynchronization with the rise edge, or the fall edge, or both the edgesof the third internal clock.
 29. The device according to claim 11,wherein the I/O circuit takes in an external data in synchronizationwith the rise edge, or the fall edge, or both the edges of the secondinternal clock, and also outputs an internal data to outside insynchronization with the rise edge, or the fall edge, or both the edgesof the third internal clock.
 30. The device according to claim 12,wherein the I/O circuit takes in an external data in synchronizationwith the rise edge, or the fall edge, or both the edges of the secondinternal clock, and also outputs an internal data to outside insynchronization with the rise edge, or the fall edge, or both the edgesof the third internal clock.
 31. A method of manufacturing asemiconductor integrated circuit device, comprising: inputting trimmingdata into a semiconductor integrated circuit device from outside andchecking trimming effects; determining the trimming data on the basis ofthe results of checking the trimming effects; programming the trimmingdata into a fuse element arranged in the semiconductor integratedcircuit device; reading out the trimming data programmed in the fuseelement to outside of the semiconductor integrated circuit device;checking whether the trimming data is programmed correctly to the fuseelement or not; and programming the trimming data into a fuse elementarranged in the semiconductor integrated circuit device once again, whenthe trimming data is not programmed correctly to the fuse element.
 32. Amethod of manufacturing a semiconductor integrated circuit device,comprising: inputting trimming data into a semiconductor integratedcircuit device from outside and checking trimming effects; determiningthe trimming data on the basis of the results of checking the trimmingeffects; programming the trimming data into a fuse element arranged inthe semiconductor integrated circuit device; reading out the trimmingdata programmed in the fuse element to outside of the semiconductorintegrated circuit device; checking whether the trimming data isprogrammed correctly to the fuse element or not; programming thetrimming data into a fuse element arranged in the semiconductorintegrated circuit device once again, when the trimming data is notprogrammed correctly to the fuse element; and carrying a product testwhen the trimming data is programmed correctly to the fuse element,wherein, when a failure is found in the product test, the trimming datais input from the outside into the semiconductor integrated circuitdevice and the trimming effects are checked once again, and the trimmingdata is determined once again on the basis of the results of checkingthe trimming effects, and the trimming data is programmed once againinto the fuse element arranged in the semiconductor integrated circuitdevice, and the trimming data programmed in the fuse element is read outonce again to the outside of the semiconductor integrated circuitdevice, then whether the trimming data is programmed correctly to thefuse element or not is confirmed once again, and if the trimming data isnot programmed correctly to the fuse element, the trimming data isprogrammed once again to the fuse element arranged in the semiconductorintegrated circuit device.